1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices having built-in voltage drop circuits.
2. Description of the Prior Art
Recently, there has been considerable activity in the research and development of increasing storage capacity and integration density. Under the above conditions, fine patterns and fine transistors are used. However, fine transistors, such as transistors having short channel lengths, do not have good resistance to hot carriers. In order to improve resistance to hot carriers, it is proposed to mount a voltage drop circuit on a chip. The voltage drop circuit functions to drop a power supply voltage externally supplied and use a dropped power supply voltage in some circuits mounted on the chip or all circuits mounted thereon.
FIG. 1 shows a conventional dynamic random access memory (DRAM) with a built-in voltage drop circuit. The DRAM shown in FIG. 1 comprises an address buffer 1, a row decoder 2, a memory cell array 3, a sense amplifier block 4, a column decoder 5, a column gate block 6, an output circuit 7, an input circuit 8, a control circuit 9 and a voltage drop circuit 10. The control circuit 9 is supplied with a row address strobe signal /RAS ("/" means an active-low signal, and /RAS is equivalent to RAS shown in FIG. 1), a column address strobe signal /CAS, and a write enable signal /WE. Din denotes input data applied to the input circuit 8, and Dout denotes output data from the output circuit 7. VCC denotes an external high-potential power supply voltage equal to, for example 5 V, and VSS denotes an external low-potential power supply voltage equal to, for example, 0 V. VII denotes a dropped voltage generated by the voltage drop circuit 10.
Row address bits A0-An are applied to the row decoder 2 via the address buffer 1, and the row decoder 2 selects one of the word lines running in the cell array 3. In this case, cells connected to the selected word line are concurrently selected, and information pieces stored in the selected cells are output to bit lines. Sense amplifiers provided in the sense amplifier block 4 respectively amplify the information pieces.
Column address bits, which are input in a time sharing process, are applied to the column decoder 5 via the address buffer 1. The column decoder 5 generates a decoded address signal for selecting one of the bit lines running in the cell array 3. The information piece connected to the selected bit line is transferred from the sense amplifier block 4 to the output circuit 7 via the column gate block 6.
The above-mentioned write and read operation is carried out in synchronism with various control signals .phi..sub.1, . . . , .phi..sub.n generated by the control circuit 9 on the basis of the row address strobe signal /RAS, the column address strobe signal /CAS, and the write enable signal /WE. The voltage drop circuit 10, which is provided separately from the control circuit 9, receives the power supply voltage VCC supplied outside of the chip, and generates the dropped voltage VII (&lt;VCC) therefrom.
FIG. 2 shows the voltage drop circuit 10 and a circuit to which the dropped voltage is applied. In FIG. 2, a sense amplifier driving circuit 11 is connected to the voltage drop circuit 10. A sense amplifier 12 is connected to a pair of bit lines BL0 and /BL0, and a sense amplifier 13 is connected to a pair of bit lines BL1 and /BL1. A memory cell 14 is connected to the bit line BL0 and a word line WL, and a memory cell 15 is connected to the bit line BL1 and the word line WL.
The voltage drop circuit 10 comprises a VCC power supply line 16, and an n-channel MOS (Metal Oxide Semiconductor) transistor (hereinafter simply referred to as an nMOS transistor) 17. The drain and gate of the nMOS transistor 17 are connected to the VCC power supply line 16. The dropped voltage VII, which is equal to VCC-Vth17 (where Vth17 is the threshold voltage of the nMOS transistor 17), is generated via the source of the nMOS transistor 17. A resistor 19 is a parasitic resistance of a wiring line 18 connecting the voltage drop circuit 10 and the sense amplifier driving circuit 11.
The sense amplifier driving circuit 11 comprises a wiring line 20 via which the dropped voltage VII is transferred, a clock input terminal 21, an inverter 22, a p-channel MOS transistor (hereinafter simply referred to as a pMOS transistor) 23, and an nMOS transistor 24. S1 denotes the output signal of the inverter 22. The clock input terminal 21 receives a sense amplifier driving circuit clock .PHI. for driving or enabling the sense amplifier driving circuit 11. When the clock .PHI. is maintained at a high (H) level, the circuit 11 turns ON the pMOS transistor 23 and the nMOS transistor 24. A sense amplifier driving voltage PSA obtained at the drain of the pMOS transistor 23 and a sense amplifier driving voltage NSA obtained at the drain of the nMOS transistor 24 drive the sense amplifiers 12 and 13.
The sense amplifier 12 includes a flip-flop made up of pMOS transistors 25 and 26, and nMOS transistors 27 and 28. The sense amplifier 13 is configured in the same manner as the sense amplifier 12. The memory cell 14 is a one-transistor-type cell, and is made up of an nMOS transistor 29 and a capacitor 30. PC denotes a cell plate voltage.
FIG. 3 is a waveform diagram showing the operation of the circuit shown in FIG. 2. The waveform diagram shown in FIG. 3 relates to the bit lines BL0 and /BL0. It will be noted that the same operation as shown in FIG. 3 will take place in other bit lines.
The word line WL is selected, and the voltage thereof increases from a low (L) level to the high level. Then, the nMOS transistor 29 is turned ON, and the bit line BL0 is connected to an internal node 31 of the cell 14. Hence, a signal quantity dependent on the ratio of the capacitance of the capacitor 30 and the parasitic capacitance of the bit line BL0 appears at the bit line BL0. Assuming that the internal node 31 of the cell 14 is at the low level, the bit line BL0 decreases by the signal quantity (approximately a few hundred mV higher than/lower than a bit line reset level, which is equal to approximately half the VCC.
Thereafter, the sense amplifier driving circuit clock .PHI. switches from the low level to the high level. In response to this change, the output signal S1 of the inverter 22 is switched from the high level to the low level, and the pMOS transistor 23 and the nMOS transistor 24 are turned ON. As a result, the sense amplifier driving voltage PSA increases to the dropped voltage VII, and the sense amplifier driving voltage NSA decreases to the VSS. In the example being considered, the internal node 31 of the cell is at the low level, and hence the potential of the bit line BL0 is lower than the potential of the bit line /BL0 by the signal quantity. Hence, the pMOS transistor 26 and the nMOS transistor 27 are turned ON, and the pMOS transistor 25 and the nMOS transistor 28 are turned OFF. Hence, the potential of the bit line BL0 decreases to the VSS, and the potential of the bit line /BL0 increases to the dropped voltage VII. In this manner, the sense amplifier 12 senses data stored in the capacitor 30.
During the sense operation of the sense amplifier 12, a current passes through the wiring line 18, the pMOS transistor 23, the pMOS transistor 26 and the bit line /BL0 in that order. The above current is large because of the characteristic of the sense amplifier 12. Hence, a large voltage drop is developed across the parasitic resistance 19 of the wiring line 18, and other circuits to which the dropped voltage VII is applied may not operate normally. The above problem is encountered in other semiconductor integrated circuit devices with built-in voltage drop circuits.